View B048K120T20_9078359.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 1 of 16 vicorpower.com 4 5 4 5 product description the v? chip bus converter module (bcm) is a high efficiency (>96%), narrow input range voltage t ransformation module (vtm) operating from a 48 vdc bus to deliver an isolated 12 v secondary for intermediate bus architecture applications. the bcm may be used to power non-isolated pol converters or as an independent 12 v source. due to the fast response time and low noise of the bcm, the need for limited life aluminum electrolytic or tantalum capacitors at the input of pol converters is reduced?r eliminated resulting in savings of board area, materials and total system cost. the bcm achieves a power density of 800 w/in 3 and may be surface mounted with a profile as low as 0.16" (4mm) over the pcb. its v? chip power package is compatible with on-board or in-board surface mounting. the v? chip package provides flexible thermal management through its low junction-to-case and junction-to-bga thermal resistance. owing to its high conversion efficiency and safe operating temperature range, the bcm does not require a discrete heat sink in typical applications. it is also compatible with heat sink options, assuring low junction temperatures and long life in the harshest environments. absolute maximum ratings p arameter values unit notes +in to -in -1.0 to 60.0 vdc +in to -in 100 vdc for 100 ms pc to -in -0.3 to 7.0 vdc tm to -in -0.3 to 7.0 vdc +out to -out -0.5 to 15.0 vdc isolation voltage 2250 vdc input to output operating junction temperature -40 to 125 ? t grade; see note 2 output current 17.0 a continuous p eak output current 25 a for 1 ms case temperature during reflow 208 ? storage temperature -40 to 150 ? output power 200 w continuous p eak output power 300 w for 1 ms thermal resistance symbol parameter typ max units r jc j unction-to-case 1.1 1.5 ?/w r jb j unction-to-bga 2.1 2.5 ?/w r ja j unction-to-ambient 3 6.5 7.2 ?/w r ja j unction-to-ambient 4 5.0 5.5 ?/w 48 v to 12 v v? chip converter ?200 watt (300 watt for 1 ms) ? igh density ?up to 800 w/in 3 ? mall footprint ?200 w/in 2 low weight ?0.5 oz (14 g) zvs/zcs isolated sine amplitude converter >96% efficiency 125? operation ? ? transient response >3.5 million hours mtbf no output filtering required bga or j-lead packages B048K120T20 1 + ? vi k + ? v in = 42 - 53 v v out = 10.5 - 13.25 v iout = 17.0 a k = 1 / 4 rout = 25 m ? max notes 1. for complete product matrix see chart on page 10. 2. the referenced junction is defined as the semiconductor having the highest temperature. this temperature is monitored by the temperature monitor (tm) signal and by a shutdown comparator. 3. B048K120T20 surface mounted in-board to a 2" x 2" fr4 board, 4 layers 2 oz cu, 300 lfm. 4. b048l120t20 (0.25"h optional pin fins) surface mounted on fr4 board, 300 lfm. actual size v? chip tm ?bcm bus converter module
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 2 of 16 vicorpower.com 4 5 specifications p arameter min typ max unit note input voltage range 42 48 53 vdc input dv/dt 1 v/? input undervoltage turn-on 42 vdc input undervoltage turn-off 37 vdc input overvoltage turn-on 53 vdc input overvoltage turn-off 59 vdc input quiescent current 1.5 1.8 ma pc low inrush current overshoot 2.9 a using test circuit in fig.22; see fig.1 input current 4.65 adc input reflected ripple current 30 50 ma p-p using test circuit in fig.22; see fig.4 no load power dissipation 2.50 3.00 w internal input capacitance 2 f internal input inductance 20 nh recommended external input capacitance 10 ? 200 nh maximum source inductance; see fig.22 input (conditions are at 48 vin, full load, and 25? ambient unless otherwise specified) figure 1 ?inrush transient current at full load and 48 vin with pc enabled figure 2 ?output voltage turn-on waveform with pc enabled at full load and 48 vin figure 3 ?utput voltage turn-on waveform with input turn-on at full load and 48 vin figure 4 ?input reflected ripple current at full load and 48 vin input waveforms
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 3 of 16 vicorpower.com 4 5 4 5 specifications, continued p arameter min typ max unit note rated dc current 0 17.0 adc p eak repetitive current 25.0 a max pulse width 1ms, max duty cycle 10%, baseline power 50% dc current limit 17.0 21.0 26.0 adc current share accuracy 5 10 % see parallel operation on page 12 efficiency 10a load 95.5 96.2 % see fig.5 full load 95.0 95.7 % see fig.5 internal output inductance 1.6 nh internal output capacitance 12 ? effective value load capacitance 1000 ? output overvoltage setpoint 14.75 vdc output ripple voltage no external bypass 95 150 mv see figs.7 and 9 1? bypass capacitor 12 mv see fig.8 av erage short circuit current 200 ma effective switching frequency 2.8 3.5 4.2 mhz fixed, 1.75 mhz per phase line regulation k 0.245 0.250 0.255 v out =k? in at no load load regulation r out 25 m ? see fig. 26 tr ansient response v oltage overshoot 230 mv 0-17.0a load step, see fig.10 40 mv 1.2-15a load step with 1? bypass, see fig. 11 response time 200 ns see figs.10 and 11 recovery time 1 ? see figs.10 and 11 output overshoot input turn-on 0 mv no output filter; see fig.3 pc enable 0 mv no output filter; see fig.2 output turn-on delay f rom application of power 250 ms no output filter; see fig.3 f rom release of pc pin 50 ms no output filter; see fig.2 output (conditions are at 48 vin, full load, and 25? ambient unless otherwise specified) efficiency vs. output power 89 90 91 92 93 94 95 96 97 050 100 150 200 output power (w) efficiency (%) 25 75 125 175 figure 5 ?efficiency vs. output power at 12 vout power dissipation 0 1 2 3 4 5 6 7 8 9 10 output power (w) power dissipation (w) 050 100 150 200 25 75 125 175 figure 6 ?ower dissipation as a function of output power output waveforms
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 4 of 16 vicorpower.com 4 5 specifications, continued figure 8 ?utput voltage ripple at full load and nominal vin with 1 f ceramic external bypass capacitor. figure 7 ?output voltage ripple at full load and 48 vin; without any external bypass capacitor. figure 9 ?output voltage ripple vs. output power at 48 vin without any external bypass capacitor. figure 10 ?0-17 a load step with 100 f input capacitance and no output capacitance. figure 11 ?17-0a load step with 100 f input capacitance and no output capacitance. v out i out 7 a/div v out i out 7 a/div
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 5 of 16 vicorpower.com 4 5 4 5 p arameter min typ max unit note primary control (pc) dc voltage 4.8 5.0 5.2 v module disable voltage 2.4 2.5 v module enable voltage 2.5 2.6 v current limit 2.4 2.5 2.9 ma source only enable delay time 50 ms see fig.2 disable delay time 4 10 s see fig.12 t emperature monitor (tm) 27? setting 2.95 3.00 3.05 v operating junction temperature t emperature coefficient 10 mv/? full range accuracy ? ? operating junction temperature current limit 100 ? source only a uxiliary pins (conditions are at nominal line, full load, and 25? ambient unless otherwise specified) figure 12 ?v out at full load vs. pc disable figure 13 pc signal during fault specifications, continued p arameter min typ max unit note mtbf mil-hdbk-217f 3.6 mhrs 25?, gb t elcordia tr-nt-000332 4.2 mhrs t elcordia sr-332 tbd hrs demonstrated tbd hrs isolation specifications v oltage 2,250 vdc input to output capacitance 5,000 6,500 pf input to output resistance 10 m ? input to output agency approvals (pending) ct?vus ul/csa 60950, en 60950 ce mark low voltage directive mechanical parameters see mechanical drawing, figs.15 and 17 w eight 0.5 / 14 oz / g dimensions length 1.26 / 32 in / mm width 0.85 / 21.5 in / mm height 0.24 / 6 in / mm general
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 6 of 16 vicorpower.com 4 5 v? chip stress driven product qualification process specifications, continued symbol parameter min typ max unit note over temperature shutdown 125 130 135 ? junction temperature thermal capacity 0.61 ws/? bga package r jc j unction-to-case thermal impedance 1.1 1.5 ?/w r jb j unction-to-bga thermal impedance 2.1 2.5 ?/w r ja j unction-to-ambient 1 6.5 7.2 ?/w r ja j unction-to-ambient 2 5.0 5.5 ?/w thermal notes 1. B048K120T20 surface mounted in-board to a 2" x 2" fr4 board, 4 layers 2 oz cu, 300 lfm. 2. B048K120T20 (0.25"h optional pin fins) surface mounted on fr4 board, 300 lfm. t est standard environment high temperature operational life (htol) jesd22-a-108-b 125?, vmax, 1,008 hrs t emperature cycling jesd22-a-104b -55? to 125?, 1,000 cycles high temperature storage jesd22-a-103a 150?, 1,000 hrs moisture resistance jesd22-a113-b moisture sensitivity level 5 t emperature humidity bias testing (thb) eia/jesd22-a-101-b 85?, 85% rh, vmax, 1,008 hrs pressure cooker testing (autoclave) jesd22-a-102-c 121?, 100% rh, 15 psig, 96 hrs highly accelerated stress testing (hast) jesd22-a-110b 130?, 85% rh, vmax, 96 hrs solvent resistance/marking permanency jesd22-b-107-a solvents a, b & c as defined mechanical vibration jesd22-b-103-a 20 g peak, 20-2,000 hz, test in x, y & z directions mechanical shock jesd22-b-104-a 1,500 g peak 0.5 ms pulse duration, 5 pulses in 6 directions electro static discharge testing ?human body model eia/jesd22-a114-a meets or exceeds 2,000 volts electro static discharge testing ?machine model eia/jesd22-a115-a meets or exceeds 200 volts highly accelerated life testing (halt) p er vicor internal operation limits verified, destruct margin determined t est specification dynamic cycling p er vicor internal constant line, 0-100% load, -20? to 125? t est specification t est standard environment bga daisy-chain thermal cycling ipc-sm-785 tc3, -40 to 125? at <10?/min, ipc-9701 10 min dwell time. ball shear ipc-9701 no failure through intermetallic. ipc j-std-029 bend test ipc j-std-029 deflection through 4 mm. v? chip ball grid array interconnect qualification
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 7 of 16 vicorpower.com 4 5 4 5 pin/control functions +in/-in ?dc voltage input ports the v? chip input voltage range should not be exceeded. an internal under/over voltage lockout-function prevents operation outside of the normal operating input range. the bcm turns on within an input voltage window bounded by the ?nput under-voltage turn-on?and ?nput over-voltage turn-off?levels, as specified. the v? chip may be protected against accidental application of a reverse input voltage by the addition of a rectifier in series with the positive input, or a reverse rectifier in shunt with the positive input located on the load side of the input fuse. the connection of the v? chip to its power source should be implemented with minimal distribution inductance. if the interconnect inductance exceeds 100 nh, the input should be bypassed with a rc damper to retain low source impedance and stable operation. with an interconnect inductance of 200 nh, the rc damper may be 10 f in series with 0.3 ? . a single electrolytic or equivalent low-q capacitor may be used in place of the series rc bypass. pc ?primary control the primary control port is a multifunction node that provides the following functions: enable/disable ?if the pc port is left floating, the bcm output is enabled. once this port is pulled lower than 2.4 vdc with respect to ?n, the output is disabled. this action can be realized by employing a relay, opto-coupler, or open collector transistor. refer to figures 1-3, 12 and 13 for the typical enable/disable characteristics. this port should not be toggled at a rate higher than 1 hz. the pc port should also not be driven by or pulled up to an external voltage source. primary auxiliary supply ?the pc port can source up to 2.4 ma at 5.0 vdc. the pc port should never be used to sink current. alarm ?the bcm contains circuitry that monitors output overload, input over voltage or under voltage, and internal junction temperatures. in response to an abnormal condition in any of the monitored parameters, the pc port will toggle. refer to figure 13 for pc alarm characteristics. tm ?temperature monitor the temperature monitor port monitors the highest junction temperature of the bcm. this output may be used to provide feedback and validation of the thermal management of v? chips, as applied in diverse power systems and environments. at 300? (+27?), the tm output is nominally 3.0 vdc. the tm output is proportional to temperature and varies at 10 mv/?. the tm accuracy is typically +/-5?. a kelvin connection to the ?n port of the bcm should be used as the ground return of the tm signal to maintain the specified accuracy. +out/-out ?dc voltage output ports t wo sets of contacts are provided for the +out port. they must be connected in parallel with low interconnect resistance. similarly, two sets of contacts are provided for the ?ut port. they must be connected in parallel with low interconnect resistance. within the specified operating range, the average output voltage is defined by the level 1 dc behavioral model of figure 26. the current source capability of the bcm is rated in the specifications section of this document. the low output impedance of the bcm, reduces or eliminates the need for limited life aluminum electrolytic or tantalum capacitors at the input of pol converters. t otal load capacitance at the output of the bcm should not exceed the specified maximum. owing to the wide bandwidth and low output impedance of the bcm, low frequency bypass capacitance and significant energy storage may be more densely and efficiently provided by adding capacitance at the input of the bcm. -in primary control rsv te m p. monitor +in -out +out -out +out bottom view a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al figure 14 ?cm bga configuration signal bga name designation +in a1-l1, a2-l2 ?n aa1-al1, aa2-al2 tm p1, p2 pc v1, v2 +out a3-g3, a4-g4, u3-ac3, u4-ac4 ?ut j3-r3, j4-r4, ae3-al3, ae4-al4
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 8 of 16 vicorpower.com 4 5 notes: 1- dimensions are . 2- unless otherwise specified, tolerances are: .x/[.xx] = +/-0.25/[.01]; .xx/[.xxx] = +/-0.13/[.005] 3- product marking on top surface inch mm 30,00 1.181 1,00 0.039 15,00 0.591 18,00 0.709 1,00 0.039 9,00 0.354 1,00 0.039 1,00 0.039 input output l l c c bottom view solder ball #a1 seating plane top view (component side) output input solder ball #a1 indicator typ 3,9 0.15 15,6 0.62 21,5 0.85 32,0 1.26 1,6 0.06 28,8 1.13 5,9 0.23 16,0 0.63 solder ball 0.51 (106) x 0.020 mechanical drawings figure 15 ? cm bga mechanical outline; in-board mounting notes: 1- dimensions are . 2- unless otherwise specified, tolerances are: .x/[.xx] = +/-0.25/[.01]; .xx/[.xxx] = +/-0.13/[.005] inch mm 15,00 0.591 17,00 0.669 20,00 0.787 13,00 0.512 16,00 0.630 24,00 0.945 8,00 0.315 16,16 0.636 8,08 0.318 18,00 0.709 1,00 0.039 9,00 0.354 0,37 0.015 29,26 1.152 (2) x 0.394 (4) x 0.236 1,00 0.039 pcb cutout +in +out1 -out1 +out2 -out2 -in rsv tm pc solder pad #a1 recommended land and via pattern (component side shown) solder mask defined pad 1,6 0.06 0,51 0.020 1,00 0.039 1,50 0.059 0,50 0.020 1,00 0.039 0,50 0.020 1,00 0.039 solder mask defined pads connect to inner layers 0,51 0.020 0,53 0.021 10,00 6,00 (106) x (4) x r ( ? ) ( ) ? plated via ( ) 31 1 figure 16 ?cm bga pcb land/via layout information; in-board mounting in-board mounting bga surface mounting requires a cutout in the pcb in which to recess the v? chip
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 9 of 16 vicorpower.com 4 5 notes: 1- dimensions are mm/[inch]. 2- unless otherwise specified, tolerances are: .x/[.xx] = +/-0.25/[.01]; .xx/[.xxx] = +/-0.13/[.005] 3- product marking on top surface. c c l l 16,00 0.630 24,00 0.945 0,45 0.018 8,00 0.315 14,94 0.588 16,94 0.667 20,00 0.787 12,94 0.509 15,99 0.630 3,01 0.118 3,01 0.118 7,10 0.280 (4) pl. 11,10 0.437 (2) pl. 6,1 0.24 32,0 22,0 0.87 bottom view output input output input top view (component side) 1.26 9,3 0.37 15,55 0.612 3.9 0.15 (elevated option) (elevated option) mechanical drawings figure 17 ? cm j-lead mechanical outline; on-board mounting notes: 1- dimensions are mm/[inch]. 2- unless otherwise specified, tolerances are: .x/[.xx] = +/-0.25/[.01]; .xx/[.xxx] = +/-0.13/[.005] 14,94 0.588 16,94 0.667 20,00 0.787 12,94 0.509 16,00 0.630 24,00 0.945 8,00 0.315 15,74 0.620 3,26 0.128 3,26 0.128 0,51 0.020 1,38 0.054 11,48 0.452 1,60 0.063 7,48 0.295 ( component side shown ) recommended land pattern -in pc rsv tm +in +out1 -out1 +out2 -out2 (4) x (6) x (2) x (2) x (2) x (2) x typ typ (8) x (2) x (2) x (2) x figure 18 ?bcm j-lead pcb land layout information; on-board mounting
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 10 of 16 vicorpower.com 4 5 4 5 part numbering and configuration options v? chip bus converter part numbering b 048 k 120 t 20 bus converter module input voltage designator product grade temperatures (?) grade storage operating t- 40 to150 -40 to125 m- 65 to 150 -55 to 125 configuration options configuration in-board* on-board* in-board with 0.25" on-board with 0.25" (package k) (package f) pin fins** pin fins** effective power density 1190 w/in 3 800 w/in 3 445 w/in 3 360 w/in 3 j unction-board 2.1 ?/w 2.4 ?/w 2.1 ?/w 2.4 ?/w thermal resistance j unction-case 1.1 ?/w 1.1 ?/w n/a n/a thermal resistance j unction-ambient 6.5 ?/w 6.8 ?/w 5.0 ?/w 5.0 ?/w thermal resistance 300lfm *surface mounted to a 2" x 2" fr4 board, 4 layers 2 oz cu **pin fin heat sink available as a separate item output voltage designator (=vout x10) output power designator (=pout/10) configuration options a= on-board elevated (fig.21) f= on-board (fig.20) k= in-board (fig.19) in?oard mount (v? chip recessed into pcb) 21.5 0.85 32.0 1.26 4.0 0.16 figure 19 ?n-board mounting ?package k mm in on?oard mount 22.0 0.87 32.0 1.26 6.3 0.25 figure 20 ?on-board mounting ?package f mm in
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 11 of 16 vicorpower.com 4 5 4 5 figure 22 ?cm test circuit f1 te m perature monitor load + 1 f ceramic c3 7 a fuse c1 10 f ceramic r2 2k ? d1 notes: source inductance should be no more than 200 nh. if source inductance is gr eater than 200 nh, additional bypass capacitance is required. c3 should be placed close to the load. d1 power good indicator will dim when a module fault is detected. tm should always be referenced to sg. sw1 enable/disable switch + 0.1 ? input reflected ripple measurement point r3 r1 c2 0.47 f 0.30 ? ceramic -in pc r sv tm +in -out +out -out +out bcm k ro configuration options (cont.) 22.0 0.87 32.0 1.26 9.5 0.37 figure 21 ?on-board elevated mounting ?package a mm in
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 12 of 16 vicorpower.com 4 5 parallel operation the bcm will inherently current share when properly configured in an array of bcms. arrays may be used for higher power or redundancy in an application. current sharing accuracy is maximized when the source and load impedance presented to each bcm within an array are equal. the recommended method to achieve matched impedances is to dedicate common copper planes within the pcb to deliver and return the current to the array, rather than rely upon traces of varying lengths. in typical applications the current being delivered to the load is larger than that sourced from the input, allowing traces to be utilized on the input side if necessary. the use of dedicated power planes is, however, preferable. the bcm power train and control architecture allow bi-directional power transfer, including reverse power processing from the bcm output to its input. reverse power transfer is enabled if the bcm input is within its operating range and the bcm is otherwise enabled. the bcms ability to process power in reverse improves the bcm transient response to an output load dump. thermal management the high efficiency of the v? chip results in relatively low power dissipation and correspondingly low generation of heat. the heat generated within internal semiconductor junctions is coupled with low effective thermal resistances, r jc and r jb , to the v? chip case and its ball grid array allowing thermal management flexibility to adapt to specific application requirements (fig. 25). case 1 convection via optional pin fins to air. if the application is in a typical environment with forced convection over the surface of the pcb and greater than 0.4" headroom, a simple thermal management strategy is to procure the optional pin fins for the v? chips. the total junction-to- ambient thermal resistance, r ja , of a surface mounted v? chip with optional 0.25" pin fins is 5?/w in 300 lfm air flow (fig.26). at full rated output power of 200 w, the heat generated by the bcm is approximately 9 w (fig.6). therefore, the junction temperature rise to ambient is approximately 45?. given a maximum junction temperature of 125?, a temperature rise of 45? allows the v? chip to operate at rated output power at up to 80? ambient temperature. at 100 w of output power, operating ambient temperature extends to 100?. case 2?onduction to the pcb the low thermal resistance junction-to-bga, r jb , allows use of the pcb to exchange heat from the v? chip, including convection from the pcb to the ambient or conduction to a cold plate. for example, with a v? chip surface mounted on a 2" x 2" area of a multi-layer pcb, with an aggregate 8 oz of effective copper weight, the total junction-to-ambient thermal resistance, r ja , is 6.5?/w in 300 lfm air flow (see thermal resistance section, page 1). given a maximum junction temperature of 125? and 9 w dissipation at 200 w of output power, a temperature rise of 59? allows the v? chip to operate at rated output power at up to 66? ambient temperature. figure 25 ?unction-to-ambient thermal resistance of bcm with 0.25" pin fins (pin fins available as a separate item.) bcm with 0.25'' optional pin fins 3 4 5 6 7 8 9 10 0 100 200 300 400 500 600 airflow (lfm) tja 0 30 60 90 120 150 180 210 -40 -20 0 20 40 60 80 100 120 140 output power operating junction temperature figure 24 ?thermal derating curve 4 5 application note figure 23 thermal resistance jc = 1.1 ?/w jb = 2.1 ?/w
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 13 of 16 vicorpower.com 4 5 4 5 4 5 application note (continued) i q + + - v out v in v i k + + ?vin ?iout 52 ma 20 m ? i out r out 1 / 4 1 / 4 l in = 20 nh = 1.6 nh + + v out c out v in v i k + + ?vin ?iout c in i out l out 20 m ? r c out 2 f 52 ma 12 f i q r out 8.5 nh 40 m ? r c in 2.0 m ? 0.3 m ? 1 / 4 1 / 4 v? chip bus converter level 1 dc behavioral model for 48 v to 12 v, 200 w v? chip bus converter level 2 transient behavioral model for 48 v to 12 v, 200 w figure 26 ?his model characterizes the dc operation of the v? chip bus converter, including the converter transfer function and its losses. the model enables estimates or simulations of output voltage as a function of input voltage and output load, as well as total converter power dissipation or heat generation. figure 27 ?his model characterizes the ac operation of the v? chip bus converter including response to output load or input voltage transients or steady state modulations. the model enables estimates or simulations of input and output voltages under transient conditions, including response to a stepped load with or without external filtering elements. the thermal resistance of the pcb to the surrounding environment in proximity to v? chips may be reduced by low profile heat sinks surface mounted to the pcb. the pcb may also be coupled to a cold plate by low thermal resistance standoff elements as a means of achieving effective cooling for an array of v? chips, without a direct interface to their case. case 3?ombined direct convection to the air and conduction to the pcb. parallel use of the v? chip internal thermal resistances (including junction-to-case and junction-to-bga) in series with external thermal resistances provides an efficient thermal management strategy as it reduces total thermal resistance. this may be readily estimated as the parallel network of two pairs of series configured resistors. the tm (temperature monitor) port monitors the v? chip junction temperature and provides feedback and validation of the thermal management of v? chips, as applied in diverse power systems and environments.
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 14 of 16 vicorpower.com 4 5 4 5 4 5 input impedance recommendations to take full advantage of the bcm capabilities, the impedance presented to its input terminals must be low from dc to approximately 5 mhz. the source should exhibit low inductance (less than 100 nh) and should have a critically damped response. if the interconnect inductance exceeds 100 nh, the bcm input pins should be bypassed with an rc damper (e.g., 8 f in series with 0.3 ohm) to retain low source impedance and stable operations. given the wide bandwidth of the bcm, the source response is generally the limiting factor in the overall system response. anomalies in the response of the source will appear at the output of the bcm multiplied by its k factor. the dc resistance of the source should be kept as low as possible to minimize voltage deviations. this is especially important if the bcm is operated near low or high line as the over/under voltage detection circuitry could be activated. input fuse recommendations v? chips are not internally fused in order to provide flexibility in power system configuration. however, input line fusing of v? chips must always be incorporated within the power system. a fast acting fuse, such as nano2 fuse 451 series 7 a 125 v, is required to meet safety agency conditions of acceptability. the input line fuse should be placed in series with the +in port. application note (continued) application circuits fpa local loop vo = v l C io ? ro -in pc r sv tm +in -out +out -out +out bcm k ro v f = vs = v l l o a d fac torized pow er bus p048k055t24al B048K120T20 48 vin (36 - 75 vdc) ( k=1/4: ro=25 m ? ) vs range = 42 ?53 vdc k +out ?ut +in ?n vc pc tm il vh pr im sg sc prm-al cp rl cd figure 29 ?he prm regulates its output to provide a constant factorized bus voltage. the output voltage is the nominal load voltage, vo, at no load and decreases with load at a constant rate equal to the bcm output resistance ro. in the following figure; k = bcm transformation ratio vf = prm output (factorized bus voltage) ro = bcm output resistance v l = desired load voltage vo = bcm output v s = prm output set point voltage -in pc r sv tm +in -out +out -out +out bcm k ro 48 vin (42 - 53 vdc) v l = 10.5 - 13.25 v nipol 1 nipol 2 nipol 3 nipol 4 load 1 load 2 load 3 load 4 figure 28 ?he bcm provides an isolated, loosely regulated output from a narrow range input ideal for driving non-isolated point of load converters (nipols)
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 15 of 16 vicorpower.com 4 5 4 5 4 5 application note (continued) v? chip soldering recommendations v? chip modules are intended for reflow soldering processes. the following information defines the processing conditions required for successful attachment of a v? chip to a pcb. failure to follow the recommendations provided can result in aesthetic and functional failure of the module. storage v? chip modules are currently rated at msl 5. exposure to ambient conditions for more than 72 hours requires a 24 hour bake at 125? to remove moisture from the package. solder paste stencil design solder paste is recommended for a number of reasons, including overcoming minor solder sphere co-planarity issues as well as simpler integration into overall smd process. 63/37 snpb, either no-clean or water-washable, solder paste should be used. pb-free development is underway. the recommended stencil thickness is 6 mils. the apertures should be 20 mils in diameter for the in-board (bga) application and 0.9-0.9:1 for the on-board (j-leaded). pick & place in-board (bga) modules should be placed as accurately as possible to minimize any skewing of the solder joint; a maximum offset of 10 mils is allowable. on-board (j-leaded) modules should be placed within 5 mils. to maintain placement position, the modules should not be subjected to acceleration greater than 500 in/sec 2 prior to reflow. reflow there are two temperatures critical to the reflow process; the solder joint temperature and the modules case temperature. the solder joints temperature should reach at least 220?, with a time above liquidus (183?) of ~30 seconds. the modules case temperature must not exceed 208? at anytime during reflow. because of the ? t needed between the pin and the case, a forced- air convection oven is preferred for reflow soldering. this reflow method generally transfers heat from the pcb to the solder joint. the modules large mass also reduces its temperature rise. care should be taken to prevent smaller devices from excessive temperatures. reflow of modules onto a pcb using air-vac-type equipment is not recommended due to the high temperature the module will experience. inspection for the bga-version, a visual examination of the post-reflow solder joints should show relatively columnar solder joints with no bridges. an inspection using x-ray equipment can be done, but the modules materials may make imaging difficult. the j-lead versions solder joints should conform to ipc 12.2 ?properly wetted fillet must be evident ? heel fillet height must exceed lead thickness plus solder thickness. removal and rework v? chip modules can be removed from pcbs using special tools such as those made by air-vac. these tools heat a very localized region of the board with a hot gas while applying a tensile force to the component (using vacuum). prior to component heating and removal, the entire board should be heated to 80-100? to decrease the component heating time as well as local pcb warping. if there are adjacent moisture-sensitive components, a 125? bake should be used prior to component removal to prevent popcorning. v? chip modules should not be expected to survive a removal operation. case temperature, 208? joint temperature, 220? 239 165 91 16 degc 183 soldering time figure 30 ?hermal profile diagram figure 31 ?properly reflowed v? chip j-lead.
v icor corporation t el: 800-735-6200 v? chip bus converter B048K120T20 rev. 2.2 page 16 of 16 vicorpower.com p/n 26575 07/04/10m 4 5 4 5 v icors comprehensive line of power solutions includes high density ac-dc and dc-dc modules and accessory components, fully configurable ac-dc and dc-dc power supplies, and complete custom power systems. information furnished by vicor is believed to be accurate and reliable. however, no responsibility is assumed by vicor for its use. v icor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction co uld result in injury or death. all sales are subject to vicors terms and conditions of sale, which are available upon request. specifications are subject to change without notice. vi cor corporation 25 frontage road ?andover, ma, usa 01810 te l: 800-735-6200, fax: 978-475-6715 email v icor express: vicorexp@vicr.com, technical support: apps@vicr.com intellectual pr oper ty notice v icor and its subsidiaries own intellectual property (issued u.s. and foreign patents and pending patent applications) relating to the product described in this data sheet including; ? the electrical and thermal utility of the v? chip package ? the design of the v? chip package the power conversion topology utilized in the v? chip package ? the control architecture utilized in the v? chip package ? the factorized power architecture. purchase of this product conveys a license to use it. however, no responsibility is assumed by vicor for any infringement of pa tents or other rights of third parties which may result from its use. except for its use, no license is granted by implication or otherwise under any patent or patent rights of vicor or any of its subsidiaries. anybody wishing to use vicor proprietary technologies must first obtain a license. potential users without a license are encouraged to first contact v icors intellectual property department. w arranty v icor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. this warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. vicor shall not be liable for collateral or consequential damage. this warranty is extended to the original purchaser only. except for the foregoing express warranty, vicor makes no warranty, express or implied, including, but not limited to, the warranty of merchantability or fitness for a particular purpose. v icor will repair or replace defective products in accordance with its own best judgement. for service under this warranty, the buyer must contact v icor to obtain a return material authorization (rma) number and shipping instructions. products returned without prior authori zation will be returned to the buyer. the buyer will pay all charges incurred in returning the product to the factory. vicor will pay all resh ipment charges if the product was defective within the terms of this warranty. information published by vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. v icor reserves the right to make changes to any products without further notice to improve reliability, function, or design. vi cor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. vicor general policy does not recommend the use of its components in life support applications wherein a failure or mal function may directly threaten life or injury. per vicor terms and conditions of sale, the user of vicor components in life support applications assu mes all risks of such use and indemnifies vicor against all damages.

▲Up To Search▲

Price & Availability of B048K120T20

	To Download B048K120T20 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .